This invention relates generally to a video processing circuit which enlarges or reduces video image in the vertical direction and, in particular, to a vertical address control at the time of writing into or reading from a video memory.
FIG. 4 is a block diagram of a video processing circuit of the prior art which enlarges or reduces video image. In the figure, 31 is a signal divider for dividing horizontal sync signal, HS, 32 is a vertical address counter, and 33 is a video memory.
Video memory 33 specifies a horizontal sync signal, HS, which forms one visual image by vertical address, and specifies each dot which is converted from analog to digital at a certain specified number of dots for each horizontal sync signal, for example 960 dots, by horizontal address.
In the case of displaying enlarged or reduced video image responding to the luminance signal stored in video memory 33, signal divider 31 divides horizontal sync signal, HS, into 1/2.sup.N and supplies the divided signal to vertical address counter 32, which controls vertical address of video memory 33, as a count up signal. Vertical address counter 32 is counted by a divided signal, and the counted value becomes the address for the vertical direction.
There is a problem, however, with the video processing circuit of the prior art in that arbitrary enlargement or reduction is absolutely impossible because in the case of writing a luminance signal into a vertical address of video memory 33 which is specified by vertical address counter 32, the reduction is only by 1/2.sup.N and in the case of reading a luminance signal from video memory 33, the reduction is also only by 1/2.sup.N.
This invention solves the foregoing problem with an objective to provide a video processing circuit which is capable of arbitrary and easy enlargement and reduction of the video signal and the resultant video image.